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ordering number : enn5228b 60200rm (ot) no. 5228-1/19 overview the STK672-050 is a stepping motor driver hybrid ic that uses power mosfets in the output stage. it includes a built-in microstepping controller and is based on a unipolar constant-current pwm system. the STK672-050 supports application simplification and standardization by providing a built-in 4 phase distribution stepping motor controller. it supports five excitation methods: 2 phase, 1-2 phase, w1-2 phase, 2w1-2 phase, and 4w1-2 phase excitations, and can provide control of the basic stepping angle of the stepping motor divided into 1/16 step units. it also allows the motor speed to be controlled with only a clock signal. the use of this hybrid ic allows designers to implement systems that provide high motor torques, low vibration levels, low noise, fast response, and high-efficiency drive. compared to the earlier sanyo stk672-010 series, the STK672-050 features a smaller package, fewer external components, and controller improvements for even higher efficiency and even higher performance microstepping motor drive. applications facsimile stepping motor drive (send and receive) paper feed and optical system stepping motor drive in copiers laser printer drum drive printer carriage stepping motor drive x-y plotter pen drive industrial robots and other stepping motor applications features can implement stepping motor drive systems simply by providing a dc power supply and a clock pulse generator. one of five drive types can be selected with the drive mode settings (m1, m2, and m3) ? phase excitation drive ?-2 phase excitation drive ?1-2 phase excitation drive ?w1-2 phase excitation drive ?w1-2 phase excitation drive provides four freely selectable modes for the vector locus during microstepping drive: circular mode, one inside mode, and two outside modes. phase retention even if excitation is switched. the excitation phase state can be verified in real time from the mo1, mo2, and moi signal output pins. the clk input counter block can be selected to be one of the following by the high/low setting of the m3 input pin. ?ising edge only ?oth rising and falling edges note*: conditions: v cc 1 = 24 v, i oh = 2.0 a, 2w1-2 drive used. continued on next page. package dimensions unit: mm 4161 1 22 60.0 67.0 16.0 5.6 25.5 11.0 (9.0) 21 2 = 42 3.6 0.5 2.0 9.0 0.4 2.9 4.0 1.0 [STK672-050] STK672-050 sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan stepping motor driver (sine wave drive) output current: 3.0 a (no heat sink * ) unipolar constant-current chopper (external excitation pwm) circuit with built-in microstepping controller thick-film hybrid ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein.
the clk and return input pins include built-in malfunction prevention circuits for external pulse noise. enable and reset pins provided. these are schmitt trigger inputs with built-in 20 k (typical) pull-up resistors. no noise generation due to the difference between the a and b phase time constants during motor hold since external excitation is used. microstepping operation supported even for small motor currents, since the reference voltage vref can be set to any value between 0 v and 1/2v cc 2. external excitation pwm drive allows a wide operating supply voltage range (v cc 1 = 10 to 45 v) to be used. current detection resistor (0.2 ) built into the hybrid ic. power mosfets for minimal driver loss motor output drive currents i oh up to 3.0 a. no. 5228-2/19 STK672-050 parameter symbol conditions ratings unit maximum supply voltage 1 v cc 1 max no signal 52 v maximum supply voltage 2 v cc 2 max no signal ?.3 to +7.0 v input voltage v in max logic input pins ?.3 to +7.0 v phase output current i oh max 0.5 seconds, single pulse, with v cc 1 applied. 4.0 a load: r = 5 , l = 10 mh for each phase. repeatable avalanche ear max 38 mj power loss pd max q c-a = 0 25 w operating temperature tc max 105 ? junction temperature tj max 150 ? storage temperature tstg ?0 to +125 ? specifications absolute maximum ratings at ta = 25? parameter symbol conditions ratings unit supply voltage 1 v cc 1 with input signals present 10 to 45 v supply voltage 2 v cc 2 with input signals present 5 ?% v input voltage v ih 0 to v cc 2v phase driver voltage handling v dss tr1, 2, 3, and 4 (the a, a, b, and b outputs) 100 (min) v phase current i oh max duty 50% 3.0 (max) a allowable operating ranges at ta = 25? parameter symbol conditions ratings unit min typ max control supply current i cc pin 7, with enable pin held low. 4.5 15 ma output saturation voltage vsat r l = 7.5 (i ? 3 a) 1.4 2.6 v average output current io ave load: r = 3.5 w/l = 3.8 mh 0.45 0.50 0.55 a for each phase, vref ? 0.6 v fet diode forward voltage vdf if = 1 a 1.2 1.8 v [control inputs] input voltage v ih except for the vref pin 4 v v il except for the vref pin 1 v input current i ih except for the vref pin 0 1 10 ? i il except for the vref pin 125 250 510 ? [vref input pin] input voltage v i pin 8 0 2.5 v input current i i pin 8 1a [control outputs] output voltage v oh i = ? ma, pins moi, mo1, mo2 2.4 v v ol i = +3 ma, pins moi, mo1, mo2 0.4 v electrical characteristics at tc = 25?, v cc 1 = 24 v, v cc 2 = 5 v continued on next page. continued from preceding page.
no. 5228-3/19 STK672-050 parameter symbol conditions ratings unit min typ max [current distribution ratio (a?)] 2w1-2, w1-2, 1-2 vref q = 1/8 100 % 2w1-2, w1-2 vref q = 2/8 92 % 2w1-2 vref q = 3/8 83 % 2w1-2, w1-2, 1-2 vref q = 4/8 71 % 2w1-2 vref q = 5/8 55 % 2w1-2, w1-2 vref q = 6/8 40 % 2w1-2 vref q = 7/8 20 % 2 vref 100 % pwm frequency fc 37 47 57 khz continued from preceding page. note: a constant-voltage power supply must be used. the design target value is shown for the current distribution ratio.
a12402 21 20 19 16 18 22 17 11 14 15 10 9 7 12 13 8 6 5 2 1 + + + + + 3 4 m1 m2 cwb clk m3 return reset moi mo1 mo2 enable sg sub pg b b a a vref m5 m4 v cc 2 excitation mode control excitation state monitor phase advance counter current distribution ratio switching pseudo-sine wave generator rise detection rc oscillator pwm control reference clock generation phase excitation drive signal generation rise/fall detection and switching internal block diagram no. 5228-4/19 STK672-050
test circuit diagrams no. 5228-5/19 STK672-050 a12403 a12406 a12405 a12404 14 9 10 8 16 22 3 4 1 2 5 6 a 15 a b b 7 + v cc 2 v cc 2 STK672-050 start vref = 2.5 v v 22 3 4 1 2 5 6 a a b b 7 v cc 1 STK672-050 v a 14 9 10 8 16 22 1 5 2 6 a abab a b sw2 sw1 b 7 18 + v cc 2 v cc 2 v cc 1 v cc 1 STK672-050 start vref = 1 v 0 v 0 v low when measuring i cc 5 v 9 22 7 a v cc 2 m1 STK672-050 10 m2 11 m3 12 m4 13 m5 14 clk 14 14 15 cwb 14 16 reset 14 17 return 14 18 enable 14 8 vref a a i il i ih vsat vdf i ih , i il ioave, icc, fc when measuring io ave: with sw1 set to ?? vref = 0.6 v when measuring fc: with sw1 set to ?? vref = 0 v when measuring icc: set enable low.
no. 5228-6/19 STK672-050 a12407 9 22 8 6 a a 7 14 14 10 14 14 11 14 14 12 14 14 13 14 14 15 14 18 16 17 19 20 21 + + v cc 2 = 5 v v cc 2 = 5 v sg 100 f or higher pg vref v cc 2 = 5 v 1 k clk enable ret reset moi mo1 mo2 v cc 1 = 10 v to 45 v two-phase stepping motor STK672-050 b b 5 2 1 3 4 a12408 0 a motor current waveform ioave i ol i oh note: this hybrid ic must be initialized with a power on reset when power is first applied. operation description 2w1-2 phase excitation drive (microstepping operation) [setting the motor current] the motor current i oh is set by the vref voltage on the hybrid ic pin 8. the following formula gives the relationship between i oh and vref. 1 i oh = vref/rs - rs: the hybrid ic internal current detection resistor (0.2 ?%) 3 applications can use motor currents from the current (0.05 to 0.1 a) set by the duty of the frequency set by the oscillator up to the limit of the allowable operating range, i oh = 3.0 a [function table] m20011 m1 0101 phase switching clock edge timing m3 1 2 phase excitation 1-2 phase excitation w1-2 phase excitation 2w1-2 phase excitation rising edge only 0 1-2 phase excitation w1-2 phase excitation 2w1-2 phase excitation 4w1-2 phase excitation rising and falling edges forward reverse cwb 0 1 aabb mo11001 mo20011 enable motor current is cut off when low reset active low
printed circuit board design recommendations this hybrid ic has two grounds, the pg pins (pins 3 and 4) and the sg pin (pin 22). these are connected internally in the hybrid ic. two power supplies are required: a motor drive supply and a 5 v supply for the hybrid ic itself. if the ground connections for these supplies are not good, the motor current waveforms may become unstable, motor noise may increase, and vibration levels may increase. use appropriate wiring for these grounds. here we present two methods for implementing these ground connections. if the grounds for the motor drive supply and the hybrid ic 5 v supply are connected in the immediate vicinity of the power supplies: if pg and sg are shorted at the power supply, connect only the pg line to pins 3 and 4 on the hybrid ic. also, be sure that no problems occur due to voltage drops due to common impedances. in the specifications, this must be v cc 2 ?%. the current waveforms will be more stable if the vref ground is connected to pin 22. for initial values, use 470 ? or over for c1 and 10 ? or over for c2. locate c1 as close to the hybrid ic as possible, and the capacitor ground line must be as short as possible. no. 5228-7/19 STK672-050 a12409 + + motor drive power supply 5 v power supply 470 f or over c1 pg sg stepping motor c2 10 f or over oscillator circuit (clk) 3 pg 4 22 14 sg clk STK672-050 7 v cc 2 8 vref a12410 motor drive power supply 5 v power supply + + 470 f or over separation c1 pg sg stepping motor c2 10 f or over 3 pg 4 22 14 sg clk STK672-050 7 v cc 2 8 vref oscillator circuit (clk) if the grounds for the motor drive supply and the hybrid ic 5 v supply are separated: insert a capacitor (c1) of 100 ? or over as close as possible to the hybrid ic. the capacitor ground line must be as short as possible. the capacitor c2 may be included if necessary. its ground line should also be as short as possible.
no. 5228-8/19 STK672-050 a12411 d1 rs l2 v cc 1 i off l1 a a mosfet and q s r 800 khz 45 khz latch circuit noise filter cr oscillator divider current divider m4 m5 vref a = 1 + enable a (control signal) i on functional description external excitation chopper drive block description since this hybrid ic adopts an external excitation method, no external oscillator circuit is required. when a high level is input to ? in the basic driver block circuit shown in the figure and the mosfet is turned on, the comparator + input will go low and the comparator output will go low. since a set signal with the pwm period will be input, the q output will go high, and the mosfet will be turned on as its initial value. the current i on flowing in the mosfet passes through l1 and generates a potential difference in rs. then, when the rs potential and the vref potential become the same, the comparator output will invert, and the reset signal q output will invert to the low level. then, the mosfet will be turned off and the energy stored in l1 will be induced in l2 and the current i off will be regenerated to the power supply. this state will be maintained until the time when an input to the latch circuit set pin occurs. in this manner, the q output is turned off and on repeatedly by the reset and set signals, thus implementing constant current control. the resistor and capacitor on the comparator input are spike removal circuit elements and synchronize with the pwm frequency. since this hybrid ic uses a fixed frequency due to the external excitation method and at the same time also adopts a synchronized pwm technique, it can suppress the noise associated with holding a position when the motor is locked. driver block basic circuit structure input pin functions pin no. symbol function pin circuit type 14 clk phase switching clock built-in pull-up resistor cmos schmitt trigger input 15 cwb rotation direction setting (cw/ccw) built-in pull-up resistor cmos schmitt trigger input 17 return forced phase origin return built-in pull-up resistor cmos schmitt trigger input 18 enable output cutoff built-in pull-up resistor cmos schmitt trigger input 9, 10, 11 m1, m2, m3 excitation mode setting built-in pull-up resistor cmos schmitt trigger input 12, 13 m4, m5 vector locus setting built-in pull-up resistor cmos schmitt trigger input 16 reset system reset built-in pull-up resistor cmos schmitt trigger input 8 vref current setting operational amplifier input
input signal functions and timing clk (phase switching clock) input frequency range: dc to 50 khz minimum pulse width: 10 ? duty: 40 to 60% (however, the minimum pulse width takes precedence when m3 is high.) pin circuit type: built-in pull-up resistor (20 k , typical) cmos schmitt trigger structure built-in multi-stage noise rejection circuit function ?hen m3 is high or open: the phase excited (driven) is advanced one step on each clk rising edge. ?hen m3 is low: the phase moves on both the rising and falling edges of the clk signal, for a total of two steps per cycle. cwb (method for setting the rotation direction) pin circuit type: built-in pull-up resistor (20 k , typical) cmos schmitt trigger structure function ?hen cwb is high: the motor turns in the clockwise direction. ?hen cwb is low: the motor turns in the counterclockwise direction. notes: when m3 is low, the cwb input must not be changed for about 6.25 ? before or after a rising or falling edge on the clk input. return (forcible return to the origin for the currently excited phase) pin circuit type: built-in pull-up resistor (20 k , typical) cmos schmitt trigger structure built-in noise rejection circuit notes: the currently excited (driven) phase can be forcibly moved to the origin by switching this input from low to high. normally, if this input is unused, it must be left open or connected to v cc 2. enable (controls the on/off state of the a, a, b, and b excitation drive outputs and selects either operating or hold as the internal state of this hybrid ic.) pin circuit type: built-in pull-up resistor (20 k , typical) cmos schmitt trigger structure function ?hen enable is high or open: normal operating state ?hen enable is low: this hybrid ic goes to the hold state and excitation drive output (motor current) is forcibly turned off. in this mode, the hybrid ic system clock is stopped and no inputs other than the reset input have any effect on the hybrid ic state. clk input acquisition timing (m3 = low) no. 5228-9/19 STK672-050 a06850 excitation counter up/down control output switching timing clk input system clock phase excitation counter clock control output timing
m1, m2, and m3 (excitation mode and clk input edge timing selection) pin circuit type: built-in pull-up resistor (20 k , typical) cmos schmitt trigger structure valid mode setting timing: applications must not change the mode in the period 5 ? before or after a clk signal rising or falling edge. m4 and m5 (microstepping mode rotation vector locus setting) ?reset (resets all parts of the system.) pin circuit type: built-in pull-up resistor (20 k , typical) cmos schmitt trigger structure function all circuit states are set to their initial values by setting the reset pin low. (note that the pulse width must be at least 10 ?.) at this time, the a and b phases are set to their origin, regardless of the excitation mode. the output current goes to about 71% after the reset is released. notes: when power is first applied to this hybrid ic, vref must be established by applying a reset. applications must apply a power on reset when the v cc 2 power supply is first applied. vref (sets the current level used as the reference for constant-current detection.) pin circuit type: analog input structure function constant-current control can be applied to the motor excitation current at 100% of the rated current by applying a voltage less than the control system power supply voltage v cc 2 minus 2.5 v. applications can apply constant-current control proportional to the vref voltage, with this value of 2.5 v as the upper limit. see page 10 for details on the current division ratio. mode setting acquisition timing no. 5228-10/19 STK672-050 m20011 m1 0101 phase switching clock edge timing m3 1 2 phase excitation 1-2 phase excitation w1-2 phase excitation 2w1-2 phase excitation rising edge only 0 1-2 phase excitation w1-2 phase excitation 2w1-2 phase excitation 4w1-2 phase excitation rising and falling edges a06851 mode switching timing excitation counter up/down clk input system clock mode setting m1 to m3 mode switching clock hybrid ic internal setting state phase excitation clock a06852 phase b phase a circular 3 2 1 m41010 m51001 mode circular a function:
no. 5228-11/19 STK672-050 output pin functions output signal functions and timing a, a, b, and b (motor phase excitation outputs) function ?n the 4 phase and 2 phase excitation modes, a 3.75 ? (typical) interval is set up between the a and a and b and b output signal transition times. mo1, mo2, and moi (phase excitation state monitors) pin circuit type: standard cmos structure function ?utput of the current phase excitation output state. moi outputs a 0 when each phase is at the origin, and outputs a 1 otherwise. current division ratios set by m3, m4, and m5 ?values provided for reference purposes. [load conditions] v cc 1 = 24 v, v cc 2 = 5 v, r/l = 3.5/3.8mh pin no. symbol function pin circuit type 19 moi phase excitation origin monitor standard cmos structure 20, 21 mo1, mo2 phase excitation state monitor standard cmos structure phase coordinate phase a phase b phase a phase b mo1 1 0 0 1 mo2 0 1 0 1 mode circular a setting m3 = 0 m3 = 1 m4 = 1 m4 = 0 m4 = 1 m4 = 1 units number of steps m5 = 1 m5 = 0 m5 = 0 m5 = 1 14 15 15 13 1/16 2w1-2 20 25 23 19 1/8 2/16 31 34 33 28 3/16 2w1-2 40 44 42 39 2/8 4/16 48 51 49 45 5/16 current 2w1-2 55 62 57 54 3/8 6/16 division 4w1-2 65 69 65 62 % 7/16 ratio 2w1-2 71 77 71 69 4/8 8/16 77 82 77 74 9/16 2w1-2 83 88 85 82 5/8 10/16 88 92 89 85 11/16 2w1-2 92 95 95 92 6/8 12/16 97 98 98 94 13/16 2w1-2 100 100 100 100 7/8 14/16
phase states during excitation switching excitation phases before and after excitation mode switching no. 5228-12/19 STK672-050 a12412 b24 24 27 28 31 3 4 5 8 11 12 15 16 19 20 25 a a a 0 16 17 1 a a b b b24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 24 26 28 30 0 2 4 6 8 10 12 14 16 18 20 22 22 23 a a b b 8 9 12 4 28 20 20 24 28 0 4 8 12 16 b24 26 28 30 a a a 0 16 18 20 22 24 28 0 4 8 12 16 20 20 28 4 12 20 28 4 0 12 16 16 18 20 22 24 25 27 29 31 1 3 5 7 9 23 22 8 24 20 10 26 18 12 16 14 28 30 6 4 2 0 11 21 13 19 15 17 24 28 0 4 8 12 16 20 26 28 30 0 2 4 6 8 10 12 14 2 4 6 b b a b a b 30 2 26 6 10 14 22 18 a b a b a b a b b a a b b 8 10 12 14 12 4 28 20 2w1-2 phase ? 2 phase 2w1-2 phase ? 1-2 phase 2w1-2 phase ? w1-2 phase w1-2 phase ? 2 phase w1-2 phase ? 1-2 phase w1-2 phase ? 2w1-2 phase 1-2 phase ? 2 phase 1-2 phase ? w1-2 phase 1-2 phase ? 2w1-2 phase 2 phase ? 1-2 phase 2 phase ? w1-2 phase 2 phase ? 2w1-2 phase 24 0 8 16 20 22 30 28 4 12 20 14 28 4 12 a b a b 29 1 25 5 9 13 21 24 28 0 4 8 12 16 20 17 a b a b 29 5 4 12 20 6 13 21 28 17 a a b a b excitation phase immediately before setting the excitation mode excitation phase according to the first clock input pulse after changing the excitation mode setting (m1 and m2)
no. 5228-13/19 STK672-050 excitation phases before and after excitation mode switching a12413 b24 23 24 25 28 29 0 1 4 5 8 9 12 13 16 17 20 21 a a a 0 16 15 31 a a b b b24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 24 26 28 30 0 2 4 6 8 10 12 14 16 18 20 22 22 23 a a b b 8 7 12 4 28 20 20 24 28 0 4 8 12 16 b24 30 a a a 0 16 22 24 28 0 4 8 12 16 20 20 28 4 12 16 28 24 20 0 4 12 16 18 20 22 24 25 27 29 31 1 3 5 7 9 23 22 8 24 20 10 26 18 12 16 14 28 30 6 4 2 0 11 21 13 19 15 17 24 28 0 4 8 12 16 20 26 28 30 0 2 4 6 8 10 12 14 6 b b a b a b 30 2 26 6 10 14 22 18 a b a b a b a b b a a b b 8 14 12 4 28 20 2w1-2 phase ? 2 phase 2w1-2 phase ? 1-2 phase 2w1-2 phase ? w1-2 phase w1-2 phase ? 2 phase w1-2 phase ? 1-2 phase w1-2 phase ? 2w1-2 phase 1-2 phase ? 2 phase 1-2 phase ? w1-2 phase 1-2 phase ? 2w1-2 phase 2 phase ? 1-2 phase 2 phase ? w1-2 phase 2 phase ? 2w1-2 phase 24 0 8 16 20 26 2 10 28 4 12 20 28 4 12 20 18 28 4 12 a b a b 30 3 27 7 11 15 23 24 28 0 4 8 12 16 20 19 a b a b 27 3 11 19 a b a b
no. 5228-14/19 STK672-050 clk cwb mosfet gate signal comparator reference voltage reset m3 m2 m1 a a b b mo1 mo2 moi 71% 100% vref a 71% 100% vref b 0 1 0 0 2 phase excitation timing chart (m3 = 1) clk cwb mosfet gate signal comparator reference voltage reset m3 m2 m1 a a b b mo1 mo2 moi 71% 100% vref a 71% 100% vref b 0 1 0 1 1-2 phase excitation timing chart (m3 = 1) 0 clk cwb mosfet gate signal comparator reference voltage reset m3 m2 m1 a a b b mo1 mo2 moi 71% 100% vref a 71% 100% vref b 0 1 1 0 w1-2 phase excitation timing chart (m3 = 1) 0 40% 40% 92% 92% clk cwb mosfet gate signal comparator reference voltage reset m3 m2 m1 a a b b mo1 mo2 moi 71% 55% 100% vref a 71% 100% vref b 0 1 1 0 2w1-2 phase excitation timing chart (m3 = 1) 0 40% 20% 40% 92% 92% 83% 55% 20% 83% 1 excitation time and timing charts clk rising edge operation
clk rising and falling edge operation no. 5228-15/19 STK672-050 clk cwb mosfet gate signal comparator reference voltage reset m3 m2 m1 a a b b mo1 mo2 moi 71% 100% vref a 71% 100% vref b 0 0 1-2 phase excitation timing chart (m3 = 0) 0 clk cwb mosfet gate signal comparator reference voltage reset m3 m2 m1 a a b b mo1 mo2 moi 71% 100% vref a 71% 100% vref b 0 0 w1-2 phase excitation timing chart (m3 = 0) 0 40% 40% 92% 92% 1 clk cwb mosfet gate signal comparator reference voltage reset m3 m2 m1 a a b b mo1 mo2 moi 71% 55% 100% vref a 71% 100% vref b 0 1 0 2w1-2 phase excitation timing chart (m3 = 0) 0 40% 20% 40% 92% 92% 83% 55% 20% 83% clk cwb mosfet gate signal comparator reference voltage reset m3 m2 m1 a a b b mo1 mo2 moi vref a vref b 0 1 0 4w1-2 phase excitation timing chart (m3 = 0) 0 1 71% 55% 65% 100% 40% 48% 20% 31% 92% 83% 77% 14% 97% 88% 71% 55% 65% 100% 40% 48% 20% 31% 92% 83% 77% 14% 97% 88%
thermal design the main elements internal to this hybrid ic with large average power losses are the current control devices, the regenerative current diodes, and the current detection resistor. since sine wave drive is used, the average power loss during microstepping drive can be approximated by applying a waveform factor of 0.64 to the square wave loss during 2 phase excitation. the losses in the various excitation modes are as follows. fclock i oh ?fclock 2 phase excitation pd 2ex = (vsat + vdf) ?i oh ?t2 + ?(vsat ?t1 + vdf ?t3) 22 fclock i oh ?fclock 1-2 phase excitation pd 1-2ex = 0.64 ?{(vsat + vdf) ?i oh ?t2 + ?(vsat ?t1 + vdf ?t3)} 44 fclock i oh ?fclock w1-2 phase excitation pd w1-2ex = 0.64 ?{(vsat + vdf) ?i oh ?t2 + ?(vsat ?t1 + vdf ?t3)} 88 fclock i oh ?fclock 2w1-2 phase excitation pd 2w1-2ex = 0.64 ?{(vsat + vdf) ?i oh ?t2 + ?(vsat ?t1 + vdf ?t3)} 16 16 fclock i oh ?fclock 4w1-2 phase excitation pd 4w1-2ex = 0.64 ?{(vsat + vdf) ?i oh ?t2 + ?(vsat ?t1 + vdf ?t3)} 16 16 here, t1 and t3 can be determined from the same formulas for all excitation methods. ? r + 0.88 ? v cc 1 + 0.88 t1 = n (1 ?i oh ) t3 = n () r + 0.88 v cc 1ri oh ?r + v cc 1 + 0.88 however, the formula for t2 differs with the excitation method. 23 2 phase excitation t2 = ?(t1 +t3) 1-2 phase excitation t2 = ?t1 fclock fclock 715 w1-2 phase excitation t2 = ?t1 2w1-2 phase excitation t2 = ?t1 fclock 4w1-2 phase excitation fclock motor phase current model figure (2 phase excitation) fclock: clk input frequency (hz) vsat: the voltage drop of the power mosfet and the current detection resistor (v) vdf: the voltage drop of the body diode and the current detection resistor (v) i oh : phase current peak value (a) t1: phase current rise time (s) v cc 1: supply voltage applied to the motor (v) t2: constant-current operating time (s) l: motor inductance (h) t3: phase switching current regeneration time (s) r: motor winding resistance (w) no. 5228-16/19 STK672-050 t3 t1 t2 i oh a12414
determine q c-a for the heat sink from the average power loss determined in the previous item. tc max: hybrid ic substrate temperature (?) ta: application internal temperature (?) pd ex : hybrid ic internal average loss (w) determine q c-a from the above formula and then size s (in cm 2 ) of the heat sink from the graphs shown below. the ambient temperature of the device will vary greatly according to the air flow conditions within the application. therefore, always verify that the size of the heat sink is adequate to assure that the hybrid ic back surface (the aluminum plate side) will never exceed a tc max of 105?, whatever the operating conditions are. next we determine the usage conditions with no heat sink by determining the allowable hybrid ic internal average loss from the thermal resistance of the hybrid ic substrate, namely 18.5 ?/w. 105 ?50 for a tc max of 105? at an ambient temperature of 50? pd ex = = 2.9 w 18.5 105 ?40 for a tc max of 105? at an ambient temperature of 40? pd ex = = 3.5 w 18.5 this hybrid ic can be used with no heat sink as long as it is used at operating conditions below the losses listed above. (see ? tc ?p d curve in the graph on page 19.) the junction temperature, tj, of each device can be determined from the loss pds in each transistor and the thermal resistance q j-c. tj = tc + q j-c pds (?) here, we determine pds, the loss for each transistor, by determining pd ex in each excitation mode. pds = pd/4 since the average loss includes the loss of the current detection resistor, we take that voltage drop into consideration in the calculation. vsat = i oh ?ron + i oh ?rs vdf = vdf + i oh ?rs the steady-state thermal resistance of a power mosfet is 5?/w. tc max ?ta q c-a = [?/w] pd ex no. 5228-17/19 STK672-050 4 0 8 12 16 20 02 4 6 8 10 12 16 14 2 1.0 3 5 7 10 2 10 2 3 5 7 100 2 3 5 pd ? q c-a guaranteed ambient temperature 60 c 40 c 50 c heat sink thermal resistance, q c-a ? c/w heat sink thermal resistance, q c-a ? c/w s ? q c-a 2 mm al plate (no surface finish) (flat black surface finish) ic internal average power loss, pd ?w heat sink surface area, s ?cm 2 no. fin 23.0( c/w) no. fin 23.0( c/w) q c ?a= ?( ( c/w) tc max = 105 c tc max ?ta pd vertical standing type natural convection air cooling
no. 5228-18/19 STK672-050 42 40 0 46 44 50 48 54 56 52 58 0 4.5 5.0 5.5 6.0 40 0 42 44 54 46 48 50 52 58 56 020 40 60 80 100 120 140 fc ? v cc 2 tc = 25 c tc = 25 c pwm frequency, fc ?khz pwm frequency, fc ?khz fc ? tc output saturation voltage, vsat ?v i oh ? vsat phase output current, i oh ?a supply voltage, v cc 2 ?v substrate temperature, tc ? c 1.5 a 2.0 a 1.0 a 0.5 a vref = 0v 2.0 a 1.0 a phase output current, i oh ?a i oh ? vdf fet diode forward voltage, vdf ?v i oh ? v cc 1 supply voltage, v cc 1 ?v substrate temperature, tc ? c motor output current, i oh ?a phase output current, i oh ?a v cc 2 = 5 v i oh ? tc 1 0 3 2 4 6 5 0123456 0 2 1 3 4 5 6 023 1456 v cc 2 = 5 v v cc 2 = 5 v v cc 2 = 5 v tc = 105 c tc = 25 c tc = 105 c tc = 25 c 0 0.5 1.5 1.0 2.0 2.5 020304050 1.0 0 2.0 3.0 10 20 40 60 80 100 120 test motor: pk264-01b test motor: pk264-02b v cc 1 = 24v v cc 2 = 5v vref = 0 v
ps no. 5228-19/19 STK672-050 this catalog provides information as of june, 2000. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer? products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer? products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?elivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. 20 30 10 40 50 60 70 80 90 100 110 100 1k 10k 50k 0.4 0.2 0 0.6 0.8 1.0 1.2 1.6 1.4 10 20 30 40 0.2 0.4 0 0.6 0.8 1.4 1.0 1.2 1.6 1.8 0 0.5 1.0 1.5 2.0 2.5 3.0 20 30 10 0 40 60 50 70 80 90 02 145 36 ? tc ? pps 2w1?ex, 4w1?ex i oh = 2.0 a w1?ex, i oh = 2.0 a 2ex i oh = 1.5 a 12ex i oh = 1.5 a v m = 45 v 2ex i oh = 1.5 a motor com current, im ?a substrate temperature increase, ? tc ? c im ? v cc 1 i oh = 2.5 a i oh = 2.0 a i oh = 1.0 a motor current setting voltage, vref ?v vref ? i motor output current, i oh, i ol, ioave ?a input pps ?hz supply voltage, v cc 1 ?v test motor: pk264-02b v cc 1 = 24 v v cc 2 = 5 v free standing with no heat sink test motor: pk264-02b tc = 25 c v cc 2 = 5 v v cc 1 = 24 v in hold mode loave i ol i oh substrate temperature increase, ? tc ? c ? tc ? p d (typ) power loss, p d ?w test motor: pk264-02b tc = 25 c v cc 2 = 5 v motor common pin current with one phase held.

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